Digital Devices Case #3 PCIe Expander 6x | Backplane & Hostcontroller
€ 1.199,00*
Direct beschikbaar, levertijd 2-5 days
The PCIe expansion system "Backplane Case #3" offers 6x PCIe slots (x4 slot, full length) in a robust desktop case.
Expand the number of PCIe slots on a motherboard of your choice with our PCIe expansion technology. Simply place the included host adapter to a free PCI Express x4 slot on your motherboard. The counterpart, the so-called client adapter, is placed on the PCI Express backplane. Now connect the two controllers with the help of the supplied data cables. The system is immediately ready for use. The backplane has a transparent PCIe switch that transparently handles the communication between the PCIe devices and the host. No drivers are needed and it works on all systems from Windows to MAC OS to Linux.
With the Case #3 you have your test equipment, which is available as PCIe hardware, directly at the place of your choice, e.g. on your desk. It might be a measurement electronics, which are used via PCIe hardware or for testing PCIe hardware.
Cable lengths from 0.8 - 5m are possible to the host system/PC.
The 200 Watt power supply is designed for continuous operation (24/7).
The built-in 120 mm fan provides optimal cooling, even with full card assembly and use in harsh industrial environments.
- Upstream: 1x PCI Express 3.0 X8
- Downstream: 6x PCI Express 3.0 X4
- Switching Capacity: 58GbpsPower
- Power consumption: 15W
- USB Connnector
- Made in Germany
| Erzielbare Datenraten | Kabel 1 | + Kabel 2 |
| PCIe Generation1 | 5 Gbit/s | 10 Gbit/s |
| PCIe Generation2 | 10 Gbit/s | 20 Gbit/s |
| PCIe Generation3 | 16 Gbit/s | 32 Gbit/s |
Note: the PCIe specification only provides PCIe x1 as a mandatory fallback
option. fallback option.
The backplane enables via USB interface diagnostics and debug information:
The API provides the following information:
- Power consumption,
- Current consumption of the 12V and 3V3 rail,
- PCIe Link Status,
- Temperature,
- Fan status,
- Eye diagram,
- PCIe slot settings
For the PCIe development are available among others:
- Transaction Layer Packet (TLP) generator for testing and
debugging of links and error handling - Real-time eye capture
- Any-to-any port mirroring for debug purposes
- External loopback at PHY and TLP layers
- Errors, statistics, performance, and TLP latency counters
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